1. Field of the Invention `The present invention relates to a data processing apparatus, and particularly to a data processing apparatus having an input/output controller for controlling interruptions.
2. Description of the Prior Art
A data processing apparatus such as a microprocessor integrated on a single semiconductor chip has in general an input/output controller which is called an interruption controller. The input/output controller of this type controls an interruption operation of a data processing apparatus. If an interruption request is generated in accordance with a certain factor, the input/output controller receives an interruption request signal and indicates generation of the interruption to a central processing unit (referred to as a "CPU" hereinafter) of the data processing apparatus. The CPU stops a program execution and then executes an interruption operation based on that factor. Thus, a variety of processes can be performed by one data processing apparatus. Therefore, the input/output control, particularly an interruption control, is one of the important features of the data processing apparatus.
Recently, several processing modes have been proposed as the input/output control mode, and the following two processing modes have been typically used in a data processing apparatus.
A first processing mode is a normal interruption mode in which information required to restart the program to be stopped by an interruption are sheltered, and thereafter the CPU executes a process corresponding to the interruption. In this mode, the CPU directly executes the interruption operation.
A second processing mode is a specific interruption mode in which the CPU stops a program execution without sheltering the information required to restart the program to be stopped. In this mode, the CPU does not directly execute an interruption operation, and therefore, the sheltering of the information is unnecessary. However, the CPU must release a signal bus and/or a memory for an interruption operation by which data is directly transferred between and input/output device (a peripheral device) and a memory. The direct memory access (DMA) is included in this second processing mode.
Many factors may occur in an application system using a data processing apparatus that require the above-mentioned input/output control (interruption control). Further, all input/output controls are not always performed in the same processing mode. Moreover, a priority order is to be assigned to a plurality of factors. That is, a variety of factors and processing modes are required in a data processing system. A general-purpose data processor, such as a microcomputer, requires that the input/output controller, which can designate the priorities and processing modes of the input/output processing at will, shall operate in accordance with an application system.
In general, the factors can be classified into external and internal ones. The external factors occur outside of a data processing apparatus and create special or a predetermined status for the apparatus; examples are proven failures and the generation of an external interruption request signal from a peripheral unit, a DMA controller, another data processing apparatus, or the like. The internal factors occur within the data processing apparatus when an internal interruption signal is generated by a source built into the data processing apparatus for example, an internal timer, an analog to digital converter, a digital to analog converter, a serial data interface unit, or the like. These internal interruption signals are generated, for example, when a predetermined time period has elapsed, when an analog/digital conversion has terminated, or when a serial data has been sent from or received at the interface unit.
In case there are a variety of the above-mentioned factors, a plurality of factors may be concurrently generated, or another factor may be generated during the processing of a certain factor. This makes it difficult to judge and control the priorities of the plural factors. For example, in an application system in which an external unit must be driven on real time when a drive signal is produced for each set time of the internal timer, the internal interruption request signal from the internal timer is to be judged with the highest priority order. In contrast, when an application system requires a high-speed data transmission between a data processing apparatus and an external peripheral unit, an external interruption request signal is to be accepted as soon as possible.
As described above, since the priorities of the input/output controls in one application are different from that of another application, the priorities must be arranged with the optimum order in the required application system.
On the other hand, with respect to the processing modes, they are also variable in the desired application systems. As to the internal timer, for instance, in the case that the driving signal to be sent to the external unit is preliminarily stored in a memory, the driving signal can be taken out of the memory according to the direct memory access (DMA) mode. While, in the case that status of a peripheral unit or an external signal is sampled at every time interval as determined by the internal timer, the CPU has to execute the sampling operation by means of the normal interruption mode.
A data processing apparatus proposed in the prior art has been expensive because it requires a complicated control circuit so as to set the priorities and processing modes of the input/output controls at will. In the low priced systems, therefore, the priorities and processing modes are frequently fixed for each factor so that they raise troubles for some applications. If, in the aforementioned examples, the internal input/output control of the internal timer is fixed at a higher priority than the external input/output control, the interruption operation would have to be deactivated in order to permit the lower priority event to be handled, for example where the data must be inputted at a high speed in response to an external input/output control request signal. On the other hand, the processing modes have been also frequently fixed at a normal interruption mode only. In the aforementioned internal timer application in which the driving signal is outputted in real time to the outside for each set time of the internal timer, the CPU execution has to be temporarily stopped in accordance with the interruption processing. Further, since the DMA mode can not be used, information relating to the CPU execution must be sheltered, and then the interruption program must be searched and read out of an instruction memory. Thus, there also arises a problem that the response time from the detection of time lapse of the internal timer to the signal output to the outside is extended.